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PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
INTRODUCTION
S5T8809 is a superior low-power-programmable PLL frequency synthesizer which can be used in high performance / Simple application for a Wide Area Pager system. S5T8809 consists of 2 kinds of divider block including a 19-bit Shift register, 16/18-bit Latch, 13/15bits R-counter and 16/18-bit NCounter, 32/33 Prescaler, and a phase detector block including a Phase detector, Lock detector and a Charge pump. S5T8809 also has a battery saving mode which can control each register block by serial control data from the -controller (MICOM) and it also boosts up signal output for fast locking.
16-TSSOP-0044
( Magnification = 1 : 4 )
FEATURES
* * * * * Maximum operating frequency: 330MHz @ 300mVP-P, VDD1 = 1.0V, VDD2 = 3.0V On-chip reference oscillator supports external crystal which oscillates up to 23MHz Superior supply current: -- FFIN = 310MHz, IDD1 = 0.8mA (Typ.) @ VDD1 = 1.0V, VDD2 = 3.0V Operating voltage: VDD1 = 0.95 to 1.5V and VDD2 = 2.0 to 3.3V Excellent Divider range: -- Ref. Divider: FRC (0): 1 / 40 to 1 / 65528 (Multiple): Default FRC (1): 1 / 5 to 1 / 32767 -- Rx Divider: PBC (0): 1 / 1056 to 1 / 65535: Default PBC (1): 1 / 1056 to 1 / 262143 * * * * * * Boost-up signal output for Fast Locking In the Standby mode, VDD1 block can be controlled by BSB Pin status -- Standby current consumption: 10A (Max.) Programmable control the output of LD to reduce internal noise Programmable 17 / 19-bit shift register value controlled by PBC Charge pump output circuitry for passive filter Package type: 16-TSSOP (0.65mm)
ORDERING INFORMATION
Device S5T8809X01-R0B0 Package 16-TSSOP-0044 Operating Temperature -25C to +75C
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S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGER
BLOCK DIAGRAM
OSCI 1 OSCO 2 VDD1 VDD2
Amp
1/8 Prescaler
13 or 15 Bit Divider ( R - counter ) FRC 13 / 15
Schmitt Trigger
16
Lock Detector
10
LD
VDD2
3
16 or 18Bit Latch 2 (Test1. LDC) Schmitt Trigger 16 / 18 Phase Detector Charge Pump 5
BSB EN DATA CLK
14 13 12 11 Shift Register * 17 or 19 Bit
PDO
Fast Lock
4
FL
18 VSS 6 16 or 18Bit Latch
Schmitt Trigger
15
FLC
18 Fin VDD1 7 8 VDD1 Amp 32/33 Prescaler 5 Bit Swallow Counter 11 or 13 bit Main Counter
POR
Schmitt Trigger
9
PBC
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PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
PIN CONFIGURATION
OSCI OSCO VDD2 FL PDO VSS Fin VDD1
1 2 3 4 5 6 7 8
16 15 14
TEST FLC BSB EN DATA CLK LD PBC
KS8809D
S5T8809
13 12 11 10 9
3
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGER
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 7 8 9 Symbol OSCI OSCO VDD2 FL PDO VSS Fin VDD1 PBC Description These input / output pins generate the reference frequency. In case of OSCI Pin, external reference frequency can be used through the AC coupling. The highest potential supply terminal that can be supplied up to 2.0 to 3.3V. Booster signal output for fast locking. The output of RX phase detector terminal for passive loop filter. There are 3-kinds of output signal states according to Rx loop error. Ground terminal Input terminal for the frequency from VCO. Output frequency from VCO was inputted through AC coupling Voltage supply terminal for Oscillator and Fin block. This pin can be supplied up to 0.95 to 1.5V from VSS. This is an input for programmable bit control which has Schmitt Trigger architecture, Internally biased pull-up. High = 16 Bits N-Divider (Default: ND0 to ND15) Low = 18 Bits N-Divider (ND0 to ND7) cf) R-divider bits will be changed by the FRC bit of program The output of phase detector can be controlled by R-counter register. When the LDC bit of R-counter set to Low, the output will be disabled to reduce a noise problem, but if it is set to High, the output will be enabled to show an lock / unlock status that is the error width between to Ref. signal and the VCO output signal. These pins are controlled by the -controller which has Schmitt Trigger architecture, Internally biased pull-down. The features of these pins are as follows; Clock input for 17 or 19-bit Shift Register, Serial data input (it include TEST1, FRC and LDC), and Latch enable input. In the BS mode (set to Low), the VDD1 block will be powered off, but the internal latch data is still valid because the VDD2 is supplied continuously. This input has Schmitt Trigger architecture & internally biased pull-up. This is the input pin for Fast Locking Control (FLC) which has Schmitt Trigger architecture, Internally biased pull-down. Low = The Current of PDO Charge pump output is Normal (Default: x1) High = The Current of PDO Charge pump output is increase (x 1.5) This is the input pin for TEST which has Schmitt trigger architecture, Internally biased Pull-down. Low = All block will be operated as normal state (Default) High = LD and FL state will be TEST mode
10
LD
11 12 13 14
CLK DATA EN BSB
15
FLC
16
TEST
4
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
ABSOLUTE MAXIMUM RATINGS
Characteristic Supply Voltage Input Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VDD1 to VDD2 VI PD TOPR TSTG Value -0.3 to +4.0 VSS -0.3 to VDD + 0.3 350 -25 to +75 -40 to +125 Unit V V mW C C
ELECTRICAL CHARACTERISTICS
(Ta = 25C, VDD1 = 1.0V, VDD2 = 3.0V, unless otherwise specified) Characteristic Operating voltage Symbol VDD1 VDD2 Operating current IDD Test Conditions - - FOSCI = 12.8MHz FFIN = 310MHz @ 0.3VP-P VDD1 = 1.0V, VDD2 = 3.0V, BSB=High VDD1 = 0.0V, VDD2 = 3.0V, BSB=Low - - - - VIH = VDD1, BSB = High VIL = 0V, BSB = High VFIN = 0.3VP-P, VDD1 = 1.0V VOSCI = 0.3VP-P, VDD1 = 1.0V VOH = 0.4V VOL = VDD2 - 0.4V VOH = 0.4V VOL = VDD2 - 0.4V - - Min. 0.95 2.0 - Typ. 1.0 3.0 0.8 Max. 1.5 3.3 - mA Unit V
Standby current Input voltage (DATA, CLK, EN, BS) Input voltage (TEST, PBC) Input current (Fin, Xin) Input frequency
ISB1 VIL VIH VIL VIH IIH IIL FFIN FOSCI IOH1 IOL1 IOH2 IOL2 ts tH
- - VDD2-0.3 - VSS1-0.2 - - 40 7 1.0 1.0 0.1 0.1 2 2
0.1 - - - - - - - 12.8 - - - - - -
10 0.3 - 0.2 - 20 20 330 23 - - - - - -
A V
V A
MHz
Output current (PDO, FL) Output current (LD) Setup-time (DATA-CLK, CLK-EN) Hold time
mA
mA S S
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S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGER
FUNCTIONAL DESCRIPTION
Table 1. N-Counter Register Program Scheme (19 bit) Bit Name Description Function ND N-Counter Data (ND 17 to ND 0) 18 Bit Program Data PBC = 1 : 16 bits (ND 15 to ND 0) will be valid PBC = 1 : 18 bits (ND 17 to ND 0) will be valid Bit 18 (ND 17) to Bit 1 (ND 0) PMC Program Mode Control 0: N-Counter Program 1: Ref. R-Counter Program Bit 0 (LSB)
PMC = 0 16/18 bit N_Counter
N_Counter Divider Data ( ND17 ~ ND0 ) PMC
DATA
MSB LSB
1 CLK
2
3
4
5
6
7
8
13
14
15
16
17
18
19
MSB : 1'st INPUT positive edge triggered
EN
Figure 1. Rx. N - Counter Register Programming Timing * * Programmable N-counter consists of 5-bits Swallow Counter, Dual modulars Prescaler and 11-bits Main Counter (if [PBC = 0], than 13-bits Main Counter) The Divide Ratio is; N = (P + 1) x S + P (M - S) = PM + S; P = Dual Modular Prescaler (32) S = 5-bits Swallow Counter value (0 to 31) M = 11-bits (PBC = High, 32 to 2047) or 13-bits (PBC = Low, 32 to 8291) N = Programmable N-Counter value (N > S) * The Main Counter can be controlled by PBC pin, when the PBC (pin 9) state set to Low, the Programmable N-counter range will be extend to 262143
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PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
*
Ex 1) In case of 16-bits program [PBC = High], Fc = 325.300MHz, Multiplier = 4, Fin = 75.975MHz [Fin Freq. / Ref. Freq.] = 75.975MHz / 6.25kHz = 1256
2
10
2 0 1 0 1 1 1 1 1 0 1
0
2 1
5
2 1 1 0 0
0
0 MSB
0 LSB
Main CNT 11 - bits
Swallow CNT 5-bits
PMC bit
NOTE: According to the above equation, 12156 / 32(P) = 379, and left = 28 that means, Swallow CNT value is "11100", Main CNT value is "379"
*
Ex 2) In case of 18-bits program [PBC = Low], Fin = 330MHz [Fin Freq. / Ref. Freq.] = [330MHz / 6.25kHz] = 52800
2 0
17
2 0
10
2 1 0 0 1 1 1 0 0 1 0
0
2 0
5
2 0 0 0 0
0
1
0 LSB
MSB
Main CNT 13 - bits Swallow CNT 5-bits
PMC bit
NOTE: The PMC bit is program mode control bit, if [0], the N-counter will be enabled
Table 2. R-Counter Register Program Scheme (19 bits) Bit Name Description RD Ref. R-Counter Data Bit 18 ~ Bit 4 LDC Lock Detector Control Bit 3 FRC Frequency of Reference Control 0: R_CNT div. = 8 x RD 1: R_CNT div. = RD (15bit) Bit 2 Bit 1 TEST 1 TEST mode control Mainly for the product Test Bit 0 (LSB) PMC Program mode control 0: ND Program 1: RD Program
Function
0: Disable 15 Bit Programmable LD out Ref. R-Counter FRC = 0 : 13 bits (RD12 to RD0) 1: Enable LD out FRC = 1 : 15 bits (RD14 to RD0)
* *
The Input Reference Frequency (X-tal Oscillator) will be divided by 1/8 Prescaler, and then divided by preprogrammed R-counter value once more. Programmable R-Counter consists of Fixed 1/8 Prescaler, 13 / 15-bits Programmable Counter When FRC = 0, Fixed 1/8 Prescaler and 13-bits counter (Min. Divide value: 5) are enabled RD = 8, R = 40 (= 8 x 5) to 65528 [Multiple 8] When FRC = 1, Fixed 1/8 Prescaler is disabled, but using 15-bits counter (Min. Divide value: 5) RD = R = 5 to 32767 [All value]
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S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGER
CONTROL MODE FOR R-COUNTER REGISTER LDC 0 1 LDC Pin State Low Normal Operation Description LDC function is independent of the other Control Bit
FRC 0 1
R-Counter Value 8 x R_cnt value (OSCI / 8 x R), Use 13 bits R-Counter R-cnt value (OSC / R), Use 15 bits R-Counter
Description FRC function is independent of the other Control Bit
TEST1 0 1 0 1
TEST 0 0 1 1
LD state Normal Normal Fn (N-CNT) Fr (N-CNT)
FL state Normal Normal High state Normal
Description * FRC is independent of the other control bit * Test is internal register control bit but, Test is external control pin * Test is related with Test, when Test = High Test Mode
PMC = 1 13/15 bit R-Counter, LDC, FRC, TEST1
R_Counter Divider Data ( RD14 ~ RD0 ) LDC FRCTEST1 DATA
MSB LSB
PMC
1 CLK
2
3
4
5
6
7
8
13
14
15
16
17
18
19
MSB : 1'st INPUT positive edge triggered
EN
Figure 2. Ref. R-Counter Register Programming Timing
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PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
*
Ex 1) FRC = 0, In case of 13bits Program, Fosc = 12.8MHz and 1/8 prescaler is used [(Osc. Freq. / Prescaler) / Ref. Freq.] = [(12.8MHz / 8) / 6.25kHz] = 256
2
12
2 0 0 0 1 0 0 0 0 0 0 0 0
0
0 MSB
0
0
0
1 LSB
LDC FRC TEST1 PMC bit R - counter 13 - bits
*
Ex 2) FRC = 1, In case of 15bits Program, Fosc = 12.8MHz and 1/8 prescaler is used [Osc. Freq. / Ref. Freq.] = [12.8MHz / 6.25kHz] = 2048
2 0
14
2 0
12
2 1 0 0 0 0 0 0 0 0 0 0 0
0
0
0
1
0
1 LSB
MSB
R - counter 15 - bits
LDC FRC TEST1 PMC bit
NOTE: The PMC bit is Program Mode Control Bit, if [1], the R-Counter will be Enabled
D0 ------------- D13
OSCI 12.8MHz 12.8MHz X-Tal
1/8 Prescaler
1.6MHz
13/15 bits Counter
Fr 6.25kHz
FRC
Figure 3. The architecture of R-Count Divider
9
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGER
DATA
tSU CLK 50%
tH
EN
tSU
50%
Figure 4. Serial DATA Input Timing
10
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
PHASE DETECTOR / LOCK DETECTOR
OSCI
1 2
1/ 8 CNT
13 or 15 Bit R- Divider
OSCO
FRC Fr LD
10
Lock Detector
Phase Detector
5 PDO 4 FL
Fn
FLC Fin
7
32/33 Counter
16 or 18 Bit N- Divider
9 PBC
Figure 5. Phase Detector / Lock Detector
Fr
Fn
PDO
Z-State
LD GND
VDD1
FL
Z-State
* Fast Lock Operation Window Window width = OSCI x 4
Figure 6. Phase Detector / Lock Detector / Fast Lock Output Waveforms
NOTES: 1. Phase detector always compares the Phase difference of N-counter with R-counter, and generates High or Low State as much as the phase difference 2. The LD output is set to Low level same as Phase detector error width
11
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGER
FAST LOCK The Fast lock can gives faster Acquisition time when the S5T8809 starts up. If Fast Lock signal was generated one time, this circuitry do not operate again even though PLL goes into unlock state. S5T8809 has two did of Fast lock; one is to control the Loop band width of Loop filter, the other is to control the charge pump current. Mode 1 Mode 2
CP2
CP1 * During CP2 operation, I pdo = I cp1 + I cp2
Phae Detector
PDO
VCO
Charge Pump
Fast Lock Phase Det.
VCO
PDO Fast Lock FL Charge Pump FL Ref. clock
FL Ref. clock
* CP1: Default charge pump output TR * CP2: When FLC = High, CP2 goes [On] state, the Timming & Phase is just same as FL signal * Mode 1 does not used FL pin, only increase PDO output current same as the width of 1'st phase error
* Exceeding a Loop Band width during Fast Lock operation * When the FLC pin set to High level, this function will be available
12
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
Fr R - Counter output Fn N - Counter output
Vdd2 Z-state
PDO
FL Ref. CLK
Vdd2
FL
Z-state Vdd2
CP2 On Time (FLC = High)
Z-state
Figure 7.
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S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGER
NOTES
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